SPIRAL Tutorial @ ASPLOS '26

Pre-Silicon and Early-Prototype Performance Estimation Using Highly Optimized Code

Overview

Emerging applications, from AI and cryptography to scientific computing, are driving a rapid proliferation of new architectures, ranging from lightweight CPU ISA extensions to fully customized accelerators. However, evaluating a new ISA or accelerator remains notoriously difficult, time-consuming, and costly: evaluators must hand-optimize application kernels for hardware whose architecture and toolchain are still evolving, often in the absence of a mature compiler, operating system, or performance analysis framework.

This tutorial introduces a systematic methodology for pre-silicon and early-prototype performance estimation that enables informed stop-or-go decisions long before complete hardware or software stacks exist. We begin with SPIRAL, a code generation system developed over 25 years through academic, industrial, and government collaborations, which automatically produces highly optimized code for emerging architectures.

We then demonstrate how to enable hardware-software co-design at the earliest stage by defining a fixed C-level function API as a stable interface between the two. Once this API is defined, SPIRAL can automatically target it and generate optimized, non-trivial kernels for benchmarking and performance evaluation. To close the loop, we introduce performance projection with proxy ISA (PISA), a fast and accurate performance estimation technique that predicts runtime performance without requiring an implemented microarchitectural model. By the end of the tutorial, attendees will understand how to use SPIRAL for early-stage performance evaluation and hands-on kernel generation for novel hardware prototypes.

📅 When: March 23, 2026, Morning Session

📍 Where: The Landing Hotel, Room TBD

Tentative Schedule

Duration	Topic	Resources
10 mins	Opening Remarks
40 mins	Session 1: Introduction to SPIRAL and Code Generation	Proc. IEEE '18 Proc. IEEE '05
40 mins	Session 2: Targeting New Architectures with Optimized Code	CGO '25
30 mins	Coffee Break ☕
40 mins	Session 3: Pre-Silicon Performance Modeling and Evaluation	MICRO '25
20 mins	Invited Talk I
20 mins	Invited Talk II
10 mins	Closing Remarks

Organizers

Naifeng Zhang

Carnegie Mellon University

Naifeng Zhang is a fifth-year Ph.D. candidate in Electrical and Computer Engineering at Carnegie Mellon University, advised by Professor Franz Franchetti. His research focuses on code generation, compilers, and programming languages. His work has earned awards at conferences such as CGO and PACT.

Franz Franchetti

Carnegie Mellon University

Franz Franchetti is the Kavčić-Moura Professor of Electrical and Computer Engineering, Associate Dean for Research in the College of Engineering, and Director of the Engineering Research Accelerator at Carnegie Mellon University. He received his Dipl.-Ing. (M.Sc.) in Technical Mathematics and Dr. techn. (Ph.D.) in Computational Mathematics from the Vienna University of Technology in 2000 and 2003, respectively. Prof. Franchetti's research focuses on automatic performance tuning and program generation for emerging parallel platforms and algorithm/hardware co-synthesis. Within the SPIRAL effort, his research goal is to enable automatic generation of highly optimized software libraries for important kernel functionality.