SPIRAL Tutorial @ ASPLOS '26

A Code Generation Approach to Hardware-Software Co-Design

Overview

Critical applications, from AI and cryptography to scientific computing, are driving the rapid proliferation of specialized hardware designs. While this trend underscores the growing importance of specialization, it also raises fundamental questions:

When is specialized hardware truly necessary, and if so, how should we efficiently explore the design space?

This tutorial presents a principled approach to hardware-software co-design based on automatic code generation. We demonstrate how generating highly optimized implementations across diverse architectures enables informed stop-or-go decisions in hardware design.

We use SPIRAL, a code generator that has been developed over 25 years and known for generating highly optimized code for a diverse range of architectures, as a central case study (Session I). The tutorial is structured around three key questions that arise throughout the co-design cycle. First, given an application domain, when do we truly need specialized hardware? (Session II). Second, do we need a full custom accelerator, or would lightweight ISA extensions suffice? (Session III). Third, if new hardware is required, how can we design and program it efficiently? (Session IV). The tutorial concludes with invited talks highlighting recent advances in compiler design for emerging architectures and their role in hardware–software co-design.

By the end of the session, attendees will gain a practical understanding of how to leverage systems such as SPIRAL to navigate hardware-software co-design and guide specialization decisions in their own domains.

📅 When: March 23, 2026, 8 AM - 12 PM

📍 Where: The Landing Hotel, Room Monogahela

Schedule

Time	Topic	Resources
8:00	Welcome & Networking 💬
8:30	Opening Remarks
8:40	Session I: Introduction to SPIRAL and Code Generation	Proc. IEEE '18 Proc. IEEE '05
	$./spiral spiral>opts := SpiralDefaults; spiral>transform := DFT(4); spiral>ruletree := RandomRuleTree(transform, opts); spiral>icode := CodeRuleTree(ruletree, opts); spiral>PrintCode("DFT4", icode, opts);
9:10	Session II: When Do We Truly Need Specialized Hardware?	CGO '25
	# Requires spiral-software/bin in $PATH $spiral < examples/mp-cuda-batch.g
9:35	Session III: Do We Need Specialized Hardware, or Just a Few More Instructions?	MICRO '25
	$make blas $make ntt
10:00	Coffee Break ☕
10:30	Session IV: How to Efficiently Design and Program Specialized Hardware?
10:55	Invited Talk by Charith Mendis Making Compilers More Evolvable With Learned Cost Models
11:20	Invited Talk by Brandon Reagen HAAC: A Hardware-Software Co-Design for Data Oblivious Processing	ISCA '23
11:45	Open Discussion & Closing Remarks

Organizers

Naifeng Zhang

Ph.D. Candidate at Carnegie Mellon University

Full bio

Naifeng Zhang is a fifth-year Ph.D. candidate in Electrical and Computer Engineering at Carnegie Mellon University, advised by Professor Franz Franchetti. His research focuses on code generation, compilers, and programming languages, and has been recognized with awards at CGO and PACT.

Franz Franchetti

Kavčić-Moura Professor at Carnegie Mellon University

Full bio

Franz Franchetti is the Kavčić-Moura Professor of Electrical and Computer Engineering, Associate Dean for Research in the College of Engineering, and Director of the Engineering Research Accelerator at Carnegie Mellon University. He received his Dipl.-Ing. (M.Sc.) in Technical Mathematics and Dr. techn. (Ph.D.) in Computational Mathematics from the Vienna University of Technology in 2000 and 2003, respectively. Prof. Franchetti's research focuses on automatic performance tuning and program generation for emerging parallel platforms and algorithm/hardware co-synthesis. Within the SPIRAL effort, his research goal is to enable automatic generation of highly optimized software libraries for important kernel functionality.

Invited Speakers

Charith Mendis

Assistant Professor at University of Illinois Urbana-Champaign

Full bio

Charith Mendis is an Assistant Professor in the Siebel School of Computing and Data Science at the University of Illinois at Urbana-Champaign. His broad research interests are at the intersection of compilers, programming languages, and machine learning. He received his Ph.D. and Master’s from the Massachusetts Institute of Technology and his B.Sc. from the University of Moratuwa. He is the recipient of the DARPA Young Faculty Award, the NSF CAREER Award, the Google ML and Systems Junior Faculty Award, the Outstanding Advisor award at UIUC, the William A. Martin Outstanding Master’s Thesis Award at MIT, and the University Gold Medal for his B.Sc. He has won numerous paper awards, including a Distinguished Paper Award at POPL, a Best Student Paper Award at the IEEE BigData conference, an honorable mention for the Best Artifact Award at SIGMOD, a Best Paper Award at ML for Systems workshop at ISCA, and an IEEE Top Picks Honorable Mention.

Brandon Reagen

Assistant Professor at New York University

Full bio

Brandon Reagen is an assistant professor of Electrical and Computer Engineering at New York University with a focus on computer architecture. He leads a group of 8 PhD students whose current focus is to make cryptographic computing practical through algorithmic, compiler, and hardware optimizations for homomorphic encryption, zero-knowledge proofs, and secure multi-party computation. Prior to cryptographic computing, he made significant contributions to accelerator design and hardware for machine learning. The work has been recognized with the ASPLOS’25 Best Paper Award, and multiple best paper nominations (DAC, PACT, HASP), and multiple Top Pick/honorable mention awards. He has further implemented many ideas, participating in multiple chip tape outs. He has several awards and recognitions including DARPA Riser and winning the NSF CAREER award. He is also now lead PI on the NSF CIRC Grand Cryptolets project and has generously received support from NSF, DARPA, Google, DTCC, and AMD.